Welcome to Iwan's FPGA Page


As I've always been interested in programmable logic / FPGA's I finally decided to buy a great Digilent Genesys2 development board.

On this page I'll publish some designs / software that can be interesting to other owners of a Genesys2 board or FPGA enthusiasts.
Digilent Genesys 2

Petalinux on Genesys 2

As the Xilinx Kintex-7™ FPGA (XC7K325T-2FFG900C) on the Genesys 2 board does not contain a hard-core processor like the ARM on the Zynq 7000 we'll make use of a Microblaze softcore processor that will be created in the FPGA. I didn't succeed in running Petalinux with the Genesys 2 demo as supplied by Digilent, so I decided to start with a new Microblaze design in Vivado.

Supported board components under Petalinux

  • UART (Using the USB UART connector)
  • 1 GBit Ethernet (Note: IP license required, trial for free available from Xilinx.)
  • On-board GPIO (8 LED's, 8 & 5 push buttons.
Please note there's still a lot work to do, but at least the above basic components are working. When I make progress I'll try to update this page with the new components.

Prerequisites

Please follow the instructions / manuals as provided by Digilent and Xilinx to install the Genesys 2 board and Vivado / Petalinux, nothing special to do here. Although other operating systems are likely to work I followed the advice of Xilinx and use CentOS 7.2 as my main Vivado / Petalinx development environment as this OS is supported by Xilinx.

Please note Vivado is (very) RAM hungry, I've had to upgrade from 6 GB to 12 GB RAM on my development system to successfully synthesize & implement the board files.

Before continuing please make sure you can synthesize and implement the demo as provided by Digilent and you can program and run it on your Genesys 2 board with the USB cable connected to the JTAG port.

Synthesize & Implement FPGA

The Vivado 2016.2 archive for the Petalinux project can be downloaded here. Sorry for the large file size (67 MB); I don't know (yet) how to package a Vivado project more efficiently.

Unzip the ZIP archive, open the XPR project file in Vivado and in the bottom left part of Vivado click on 'Generate Bitstream'. Now take a cup of coffee or maybe even a beer if you do not do this for work like me, and have some patience... On my (too) old system it will take at least 30 minutes.

After completion, select in the Vivado menu File -> Export -> Export Hardware and select in the export dialog 'Include Bitstream'.

If you encounter problems, make sure you are really using Vivado version 2016.2. Under Linux you can easily switch from one to another version of Vivado by using the source settings64.sh command in the installation folder of Vivado.

Also make sure you're not running low on RAM, at my first attempts Vivado didn't always succeed in synthesizing & implementation and seemed unreliable but after upgrading RAM those problems went away.

Building Petalinux

Now the Microblaze softcore processor and other hardware is available in a .bit file after completing the previous step the fun part comes, configuring and building Linux for the Genesys 2 board.

Although building Linux for the Microblaze is performed much faster as the hardware implementation in the previous step there are some more commands and configuration involved, as explained below.

Create project

Create a new Peatlinux project, in my case I decided to call it blazetest3.

petalinux-create --type project --template microblaze --name blazetest3

Now import the hardware definitions as just implemented in Vivado.

cd blazetest3
petalinux-config --get-hw-description=../petablaze3/petablaze3.sdk

The hardware definitions will now be imported and a Linux System Configuration Dialog will appear. You can quit this dialog without doing any modifications, and save the new configuration. Please ignore the warning messages WARNING: Only boolean type can have empty value. Fail to add driver(axi_ethernet_0) property(axififo-connected) type(reference) value().

Ethernet PHY configuration

Replace the file in subsystems/linux/configs/device-tree/system-top.dts file with this system-top.dts file. Although you can skip this step no ethernet connection will be available and you'll see some errors during the boot of Petalinux.

Build Petalinux

Execute the following command to build your Petalinux image. It will take some time, but quite fast compared to the synthesises in Vivado. If you're near a coffee bar I'll advise an espresso instead a cafe Lungo.

petalinux-build

Packaging

Almost done! We'll now combine the Genesys 2 hardware (.bit file) with the Petalinux image and create a new download.bit file that can be programmed on the Genesys 2 board.

petalinux-package --boot --fpga images/linux/system_wrapper.bit --u-boot --kernel
petalinux-package --prebuilt --fpga download.bit

Booting Petalinux

Use the following command to boot Petalinux on your Genesys 2 board. Make sure you've connected the UART port on the Genesys 2 board to your host system, and open a serial terminal like Putty to see the boot progress and get a login prompt :-) The Petalinux UART is configured at 115200 baud.

petalinux-boot --jtag --prebuilt 3 -v

As it may take some time (at my system +/- 5 minutes) to transfer the Petalinux image I'm using the -v (verbose) command line switch to see the progress of the upload. The JTAG programming time of Petalinux can be significantly decreased by using a TFTPD and / or NFS server, this is explained in detail in the Petalinux documentation from Xilinx.
Petalinux on Kintex 7 (Microblaze)

Questions / Problems?

If you have any questions or problems regarding the FPGA please do not E-mail me directly. I'm not affilated with Digilent or Xilinx. Instead, post your questions and or remarks on the Digilent Forum so others can also benefit from your question and / or solutions.

References

PetaLinux Tools Documentation, Reference Guide (UG1144 (v2014.4) November 25, 2014)


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